论文信息 - Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM

Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM

A 512Mb graphics DRAM device uses phase-tolerant read and write latency control to achieve 2Gb/s/pin GDDR3 and 2.5G/ps/pin GDDR4 operation. The IC is implemented in a 95nm 1.5V triple metal CMOS process.

Brian Johnson | Feng Lin | Brent Keeth | Hua Zheng

[1] T. Takahashi,et al. A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer , 2002, VLSIC 2002.