An optimally self-biased threshold-voltage extractor

A novel threshold-voltage extractor architecture is presented. A differential-difference transconductor (DDT) loop automatically biases the device-under-test in continuous time around the inflection point of the /spl radic/I/sub D/ vs. V/sub GS/ characteristics. Another DDT operates as an arithmetic processor to precisely implement multiplication-by-2 and subtraction as needed for extrapolation. The extraction procedure thus complies entirely with all steps of the manual saturation method. With appropriate modifications, the architecture can also serve as an extractor implementing the linear method. The proposed architecture is applicable to both PMOS and NMOS on the same chip, and generates the value of V/sub T/ as a voltage with respect to the appropriate rail. It has been fabricated on silicon, and its accuracy has been experimentally verified by comparing automatically and manually extracted parameter values.

[1]  Mohammed Ismail,et al.  A wide range differential difference amplifier: a basic block for analog signal processing in MOS technology , 1993 .

[2]  Chong-Gun Yu,et al.  An accurate and matching-free threshold voltage extraction scheme for MOS transistors , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[3]  Siew Kuok Hoon,et al.  An accurate self-bias threshold voltage extractor using differential difference feedback amplifier , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[4]  Mark G. Johnson,et al.  An input-free V/sub T/ extractor circuit using a two-transistor differential amplifier , 1993 .

[5]  I. M. Filanovsky.  Input-Free VTP and - VTN Extractor Circuits Realized on the Same Chip , 1999 .

[6]  Beomsup Kim,et al.  Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach , 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

[7]  Z. Wang,et al.  A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance , 1991 .

[8]  Andrea Baschirotto,et al.  Accurate MOS threshold voltage detector for bias circuitry , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[9]  Z. Wang,et al.  Automatic V/sub T/ extractors based on an n*n/sup 2/ MOS transistor array and their application , 1992 .