Low-power approximate MAC unit

Sacrificing exact calculations to improve digital circuit performance is at the foundation of approximate computing. In this paper, an approximate multiply-and-accumulate (MAC) unit is introduced. The MAC partial product terms are compressed by using simple OR gates as approximate counters; moreover, to further save energy, selected columns of the partial product terms are not formed. A compensation term is introduced in the proposed MAC, to reduce the overall approximation error. A MAC unit, specialized to perform 2D convolution, is designed following the proposed approach and implemented in TSMC 40nm technology in four different configurations. The proposed circuits achieve power savings more than 60%, compared to standard, exact MAC, with tolerable image quality degradation.

[1]  Davide De Caro,et al.  Design of Fixed-Width Multipliers With Linear Compensation Function , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Wei Han,et al.  A Flexible Low Power DSP With a Programmable Truncated Multiplier , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[4]  Kaushik Roy,et al.  Analysis and characterization of inherent application resilience for approximate computing , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[5]  Andrew Zisserman,et al.  Return of the Devil in the Details: Delving Deep into Convolutional Nets , 2014, BMVC.

[6]  Alessandro Cilardo,et al.  High Speed Speculative Multipliers Based on Speculative Carry-Save Tree , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Mark Horowitz,et al.  1.1 Computing's energy problem (and what we can do about it) , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[8]  Fabrizio Lombardi,et al.  An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders , 2015, IEEE Transactions on Computers.

[9]  Davide De Caro,et al.  Variable Latency Speculative Han-Carlson Adder , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Qiang Xu,et al.  Approximate Computing: A Survey , 2016, IEEE Design & Test.

[11]  Davide De Caro,et al.  Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs , 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

[12]  Davide De Caro,et al.  Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Alexandre Yakovlev,et al.  Energy-efficient approximate multiplier design using bit significance-driven logic compression , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.