High Performance Memory Access Scheduling Using Compute-Phase Prediction and Writeback-Refresh Overlap

In this paper, we propose two novel memory access scheduling algorithms: (1) Compute-Phase Prediction and (2) Writeback-Refresh Overlap. Compute-Phase Prediction is a fine-grain thread-priority prediction technique. It estimates the execution phase of the thread, whether computeintensive or memory-intensive with fine granularity, and gives higher priority to the read requests from the thread in the compute-intensive phase. Writeback-Refresh Overlap issues pending write commands and a refresh command of a rank of multi-rank DRAM system at a time, so that a rank of DRAM is refreshed while the memory bus is occupied by the write requests of the other ranks. This eliminates the idle time of the memory bus on a multi-rank DRAM system because the memory controller issues write requests for the rank that is not refreshing during the time the other rank is refreshing. We implement both features on an optimized memory access controller, which uses a 2469B budget. We evaluate the optimized memory controller using the memory scheduling championship framework. The optimized memory controller improves the execution time by 7.3%, the energy-delay product by 13.6% and the performance-fairness product by 12.2% over the baseline memory controller.