Optimization of a LNA Using Genetic Algorithm

In this paper an accurate method is presented for determining of the device sizes in a RF circuit based on ge- netic algorithm (GA). HSPICE RF simulation is used for evaluating of the fitness of the circuit specifications per every iteration of the GA. Also an example for a LNA is presented for evaluating of non-dominated sorting genetic algorithm (NSGA-II) as a method of multi objective genetic algorithm optimization. Simulation results confirm efficiency of the GA for determining of the devices sizes and optimization in a RF circuit.

[1]  Eckart Zitzler,et al.  Evolutionary algorithms for multiobjective optimization: methods and applications , 1999 .

[2]  Sang-Gug Lee,et al.  A 5.2GHz LNA in 0.35µm CMOS utilizing inter–stage series resonance and optimizing the substrate resistance , 2002 .

[3]  El-Sayed M. El-Alfy.  Flow-based path selection for Internet traffic engineering with NSGA-II , 2010, 2010 17th International Conference on Telecommunications.

[4]  Hung-Wei Chiu,et al.  A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption , 2005, IEEE Transactions on Microwave Theory and Techniques.

[5]  Habib Rajabi Mashhadi,et al.  Automating the Design of Ultra-Low-Voltage, Low-Power Analog Integrated Circuits using Improved Non-dominated Sorting Genetic Algorithm , 2009 .

[6]  Bingxue Shi,et al.  Comprehensive analysis and optimization of CMOS LNA noise performance , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[7]  D.J. Allstot,et al.  A g/sub m/-Boosted Current-Reuse LNA in 0.18/spl mu/m CMOS , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[8]  Huey-Ru Chuang,et al.  A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiver , 2003 .

[9]  Huey-Ru Chuang,et al.  A 5.7-GHz 0.18-μm CMOS gain-controlled differential LNA with current reuse for WLAN receiver , 2003, IEEE Microwave and Wireless Components Letters.

[10]  Ehsan Kargaran,et al.  A 5.7GHz low noise figure ultra high gain CMOS LNA with inter stage technique , 2010, IEICE Electron. Express.

[11]  E. H. Westerwick.  A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure , 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

[12]  O. Shoaei,et al.  Design optimization of analog integrated circuits using simulation-based genetic algorithm , 2003, Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on.

[13]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[14]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[15]  Sina Balkir,et al.  A compact optimization methodology for single-ended LNA , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).