For the intermediate circuit and method of dram

Discloses a method for the intermediate circuit and a DRAM refresh hiding for conflict. Intermediate circuit is connected to the user interface and the working operation of the first clock CLK1 to the second clock CLK2 between the DRAM and comprising: a first control circuit that generates an output enable signal CON command based on the second clock, data read enable a duration of a first state and a DRN proportional signal refresh enable signal REFN, wherein the signal CON and having a second state is equal to the CLK2 / (CLK1 CLK2?), a signal opposite to the signal CON REFN state for refreshing the DRAM; command buffer , memory access from the user interface receives a command, in response to a first state signal CON to output the access commands to the DRAM memory; a data buffer, in response to data read from the DRAM to the first state signal DRN and outputs the read data to the user interface. Use of the intermediate circuit and method of embodiments of the present invention, can be hidden conflicts DRAM refresh so that the user interface to obtain a fixed access latency.