High-performance extendable instruction set computing

In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset and immediate operands can be extended to 32 bits via the operation of an extension flag. The code density of the EISC instruction set and its memory transfer performance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems. The compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. This paper suggests a mechanism by which these dependencies might be removed in hardware.

[1]  Trevor Mudge,et al.  Code Compression for DSP , 1998 .

[2]  T.H. Lee,et al.  A 600 MHz superscalar RISC microprocessor with out-of-order execution , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[3]  David A. Patterson,et al.  Reduced instruction set computers , 1985, CACM.

[4]  Trevor Mudge,et al.  Fast Software-managed Code Decompression , 1999 .

[5]  Andrew Wolfe,et al.  Executing compressed programs on an embedded RISC architecture , 1992, MICRO 1992.

[6]  Liam Goudge,et al.  Embedded control problems, Thumb, and the ARM7TDMI , 1995, IEEE Micro.

[7]  Dezsö Sima.  Superscalar instruction issue , 1997, IEEE Micro.

[8]  James R. Goodman,et al.  Limited bandwidth to affect processor design , 1997, IEEE Micro.

[9]  Reinhold Weicker,et al.  Dhrystone: a synthetic systems programming benchmark , 1984, CACM.

[10]  Ching-Te Chuang,et al.  A 400 MHz S/390 microprocessor , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[11]  M. Kozuch,et al.  Compression of embedded system programs , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[12]  V. Moldenhauer,et al.  A 533-MHz BiCMOS superscalar RISC microprocessor , 1997 .

[13]  Manfred Schlett.  Trends in Embedded-Microprocessor Design , 1998, Computer.

[14]  R. Allmon,et al.  High-performance microprocessor design , 1998, IEEE J. Solid State Circuits.