Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations

We describe a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select, and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits. The resulting test sequences can be applied using conventional test application schemes that support limited scan operations.

[1]  Akihiro Yamamoto,et al.  Parity-scan design to reduce the cost of test application , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[3]  Irith Pomeranz,et al.  Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Ralph Marlett,et al.  Selectable Length Partial Scan: A Method to Reduce Vector Length , 1991, 1991, Proceedings. International Test Conference.

[5]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[6]  Irith Pomeranz,et al.  SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[7]  Irith Pomeranz,et al.  Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Chauchin Su,et al.  A serial scan test vector compression methodology , 1993, Proceedings of IEEE International Test Conference - (ITC).

[9]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[10]  Paolo Prinetto,et al.  New static compaction techniques of test sequences for sequential circuits , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[11]  Irith Pomeranz,et al.  On static compaction of test sequences for synchronous sequential circuits , 1996, DAC '96.

[12]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  Irith Pomeranz,et al.  Vector restoration based static compaction of test sequences for synchronous sequential circuits , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[14]  Irith Pomeranz,et al.  Techniques for improving the efficiency of sequential circuit test generation , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[15]  Kewal K. Saluja,et al.  Test application time reduction for sequential circuits with scan , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[17]  Kozo Kinoshita,et al.  Reduced scan shift: a new testing method for sequential circuits , 1994, Proceedings., International Test Conference.

[18]  Irith Pomeranz,et al.  Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Chen-Shang Lin,et al.  Test time reduction in scan designed circuits , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[20]  Jhing-Fa Wang,et al.  Overall consideration of scan design and test generation , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[21]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[23]  J.H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[24]  Dhiraj K. Pradhan,et al.  A design for testability scheme to reduce test application time in full scan , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[25]  Irith Pomeranz,et al.  Static Test Compaction for Scan-Based Designs to Reduce Test Application Time , 2000, J. Electron. Test..

[26]  Irith Pomeranz,et al.  Simulation based test generation for scan designs , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[27]  Kewal K. Saluja,et al.  An algorithm to reduce test application time in full scan designs , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[28]  S.T. Chakradhar,et al.  Static compaction using overlapped restoration and segment pruning , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).