Impact of Low-K Intra-layer Dielectrics on Integration

In deep sub-micron technologies, capacities of coupling between lines can reach values where one cannot ignore the amplitude of the noise due to this coupling. In this paper we highlight the impact of the use of various dielectric materials, to reduce the coupling capacitances, and we will study its impact on crosstalk reduction. From an analytic expression for crosstalk evaluation, one can predict that using a low-k dielectric equal to two one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.

[1]  L. Gal,et al.  On-chip cross talk-the new signal integrity challenge , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[2]  Masakazu Shoji,et al.  Theory of CMOS Digital Circuits and Circuit Failures , 1992 .

[3]  D. Deschacht,et al.  Inductance effect in interconnect coupling noise , 2001 .

[4]  Miquel Roca,et al.  Inductance in VLSI interconnection modelling , 1998 .

[5]  G. Servel,et al.  On-chip crosstalk evaluation between adjacent interconnections , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

[6]  Ibrahim N. Hajj,et al.  An analytical model for delay and crosstalk estimation with application to decoupling , 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

[7]  Lei He,et al.  An efficient inductance modeling for on-chip interconnects , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[8]  Andrew B. Kahng,et al.  Noise and delay uncertainty studies for coupled RC interconnects , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[9]  Keshab K. Parhi,et al.  Efficient crosstalk estimation , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[10]  Jason Cong,et al.  Improved crosstalk modeling for noise constrained interconnect optimization , 2001, ASP-DAC '01.

[11]  G. Servel,et al.  Impact of low-k on crosstalk [deep sub-micron technologies] , 2002, Proceedings International Symposium on Quality Electronic Design.

[12]  Malgorzata Marek-Sadowska,et al.  Modeling Crosstalk in Resistive VLSI Interconnections , 1999, VLSI Design.