High speed deficit round robin ASIC in ATM/Ethernet bridge

This paper presents a deficit round robin (DRR) application specific integrated circuit (ASIC), which is fabricated in a standard TSMC 0.18μm 1P6M technology. The proposed DRR ASIC not only replaces the first-in-first-out (FIFO) queue with DRR, but also improves the performance of ATM/Ethernet bridge with a fair queue in very-high-bit-rate digital subscriber line (VDSL). In the proposed DRR queue, two data formats, 4-bit and 8-bit widths, are studied. Notify that the average waiting time increases if the input queue works with small data format. According to the simulation result, the proposed DRR ASIC performs with the fault coverage of 99.5 % and the logic elements of 5,978 at the operating frequency of 50 MHz, the supplied voltage of 1.8 V and the power consumption of 90.1 mW; and that the chip area of the proposed DRR ASIC is 1.2×1.2 mm2 involving pads.