The phase-locked loop (PLL) circuit used in the timing recovery of high-speed digital communications and high-density digital recordings must have a fast pull-in time and low jitter. One way to satisfy both characteristics is to use a two-mode PLL in which the loop gain is switched in the pull-in state and the steady state. However, in the PLL with a conventional procedure, the time constant of the loop filter cannot be reduced in the pull-in state; hence the time for phase locking after frequency locking cannot be reduced.
This paper proposes a method in which the time constant of the loop filter and the loop gain are both switched. The loop gain is switched by the gain of the smoothing filter to eliminate ripple in the output from the phase comparator while the time constant is switched by the resistor in the loop filter. This method realizes a pull-in time one-tenth that in the PLL with conventional two-mode operation.
A PLL IC using the forementioned method was fabricated by 2-μm BiCMOS process technology. Its capture range was ±2 percent, the pull-in time was 100 μs, and the noise bandwidth was 128 kHz in 64-MHz operation.
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