Design and VLSI implementation of a Low Probability of Error Viterbi Decoder
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C. Arun | V. Rajamani | C. Arun | V. Rajamani
[1] Chi-Ying Tsui,et al. Low power soft output Viterbi decoder scheme for turbo code decoding , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[2] Russell Tessier,et al. Recon.gurable Computing and Digital Signal Processing: Past, Present, and Future , 2001 .
[3] Gerhard Fettweis,et al. A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation , 1996, IEEE Trans. Very Large Scale Integr. Syst..
[4] Teresa H. Meng,et al. A 140-Mb/s, 32-state, radix-4 Viterbi decoder , 1992 .
[5] Andries P. Hekstra,et al. An alternative to metric rescaling in Viterbi decoders , 1989, IEEE Trans. Commun..
[6] John G. Proakis,et al. Digital Communications , 1983 .
[7] Herman Schmit,et al. Hidden Markov modeling and fuzzy controllers in FPGAs , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[8] David Haccoun,et al. Adaptive Viterbi decoding of convolutional codes over memoryless channels , 1997, IEEE Trans. Commun..
[9] Thomas Noll,et al. Implementation of scalable power and area efficient high-throughput Viterbi decoders , 2002 .
[10] A. N. Willson,et al. Low-power Viterbi decoder for CDMA mobile terminals , 1998 .
[11] Javier D. Bruguera,et al. High-performance VLSI architecture for the Viterbi algorithm , 1997, IEEE Trans. Commun..
[12] Teresa H. Meng,et al. A 1-Gb/s, four-state, sliding block Viterbi decoder , 1997, IEEE J. Solid State Circuits.
[13] Masato Mizoguchi,et al. Very Low Power Consumption Viterbi Decoder LSIC Employing SST Scheme for Multimedia Mobile Communications , 1994 .
[14] Stanley J. Simmons,et al. Breadth-first trellis decoding with adaptive effort , 1990, IEEE Trans. Commun..
[15] Liang-Gee Chen,et al. IC design of an adaptive Viterbi decoder , 1996 .