论文信息 - A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology

A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology

A 2-to-5GHz multi-phase multi-period-locked DLL is fabricated in a 90nm CMOS technology. At 5GHz, the measured rms jitter is 0.874ps and the peak-to-peak jitter is 7.56ps. The multi-phase DLL is used for a 40GHz clock generator. The core area is 0.374times0.326mm2 and the power consumption is 45mW at 1V.

Shen-Iuan Liu | Chi-Nan Chuang

[1] Shen-Iuan Liu,et al. A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[2] P. R. Gray,et al. A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000 .

[3] K. Nakamura,et al. A CMOS 50% duty cycle repeater using complementary phase blending , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[4] Keng-Jan Hsiao,et al. The design and analysis of a DLL-based frequency synthesizer for UWB application , 2006 .