CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture

Abstract Multiple memory stacks can be integrated with a processor chip in the silicon interposer technology (“2.5D” stacking). In 2.5D architecture, there are two different network layers for both coherence and memory traffic. The CPU layer is used for coherence Core-to-Core traffic, while the interposer layer is associated with Core-to-Memory blocks traffic regularly. A load balancing strategy balances the traffics on the two network layers and optimizes the resources utilization. In the aforementioned strategy, after detecting congestion in the CPU layer, packets can be moved to the interposer one. It can be concluded that this transferring encounters the bottleneck of the edge portion that is connected to memory blocks. In this paper, we propose a Controlled Load Balancing Mechanism (CLBM) which efficiently controls bottleneck in load balancing methods. As a result, the CLBM selects an appropriate network based on the destination address without comparing latencies of two networks. Moreover, a multicast fault-tolerant ring is introduced to propagate network congestion information. The experimental results showed that, as compared with the absence of load balancing method and traditional load balancing strategy, our CLBM strategy achieves 37.82% and 17.22% average latency improvements and 22.19% and 8.55% average total power with minor overhead.

[1]  Chita R. Das,et al.  A novel dimensionally-decomposed router for on-chip communication in 3D architectures , 2007, ISCA '07.

[2]  Sudhir K. Satpathy,et al.  Catnap: energy proportional multiple network-on-chip , 2013, ISCA.

[3]  Natalie D. Enright Jerger,et al.  NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[4]  Jun Yang,et al.  A low-radix and low-diameter 3D interconnection network design , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[5]  Patrick Dorsey.  Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency , 2010 .

[6]  Giovanni De Micheli,et al.  CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[7]  Chen Sun,et al.  DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[8]  Pedro Javier García,et al.  ICARO: Congestion isolation in networks-on-chip , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[9]  Natalie D. Enright Jerger,et al.  Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems , 2015, MEMSYS.

[10]  Lu Wang,et al.  Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture , 2016, ACA.

[11]  Stephen W. Keckler,et al.  Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[12]  Nan Jiang,et al.  A detailed and flexible cycle-accurate Network-on-Chip simulator , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[13]  Mahmut T. Kandemir,et al.  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[14]  Lu Wang,et al.  DLL: A dynamic latency-aware load-balancing strategy in 2.5D NoC architecture , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

[15]  Sachhidh Kannan,et al.  Highly-scalable 3D CLOS NOC for many-core CMPs , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[16]  Xiaowei Li,et al.  Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[17]  Yuan Xie,et al.  Architectural benefits and design challenges for three-dimensional integrated circuits , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[18]  Chita R. Das,et al.  MIRA: A Multi-layered On-Chip Interconnect Router Architecture , 2008, 2008 International Symposium on Computer Architecture.