Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

[1]  G. Ng,et al.  (Invited) SiGe and III-V Materials and Devices: New HEMT and LED Elements in 0.18-Micron CMOS Process and Design , 2016 .

[2]  V. Djara,et al.  Low Dit HfO2/Al2O3/In0.53Ga0.47As gate stack achieved with plasma-enhanced atomic layer deposition , 2015 .

[3]  Erik Lind,et al.  Radio-Frequency Characterization of Selectively Regrown InGaAs Lateral Nanowire MOSFETs , 2014, IEEE Transactions on Electron Devices.

[4]  Cyrille Le Royer,et al.  3D monolithic integration , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[5]  T. Irisawa,et al.  Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[6]  Chuan Seng Tan,et al.  Monolithic integration of III–V HEMT and Si-CMOS through TSV-less 3D wafer stacking , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[7]  S. Takagi,et al.  High mobility III–V-on-insulator MOSFETs on Si with ALD-Al2O3 BOX layers , 2010, 2010 Symposium on VLSI Technology.

[8]  K. Y. Lee,et al.  High performance In0.53Ga0.47As FinFETs fabricated on 300 mm Si substrate , 2016, 2016 IEEE Symposium on VLSI Technology.

[9]  Meng-Fan Chang,et al.  Low-cost and TSV-free monolithic 3D-IC with heterogeneous integration of logic, memory and sensor analogy circuitry for Internet of Things , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[10]  H. Grampeix,et al.  300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology , 2016 .

[11]  Kang Yang,et al.  Envelope Tracking RF Power Amplifiers: Fundamentals, Design Challenges, and Unique Opportunities Offered by LEES-SMART InGaAs-on-CMOS Process , 2016 .

[12]  P. Hashemi,et al.  Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[13]  Lukas Czornomaz,et al.  Towards large size substrates for III-V co-integration made by direct wafer bonding on Si , 2014 .

[14]  Lukas Czornomaz,et al.  CMOS-Compatible Replacement Metal Gate InGaAs-OI FinFET With $I_{ON}=156~\mu \text{A}/\mu \text{m}$ at $V_{DD}= 0.5$ V and , 2016, IEEE Electron Device Letters.

[15]  Kevin K. H. Chan,et al.  Strained Si1−xGex-on-insulator PMOS FinFETs with excellent sub-threshold leakage, extremely-high short-channel performance and source injection velocity for 10nm node and beyond , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[16]  E. Leobandung,et al.  Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution , 2013, 2013 IEEE International Electron Devices Meeting.

[17]  M. J. W. Rodwell,et al.  Record Ion (0.50 mA/µm at VDD = 0.5 V and Ioff = 100 nA/µm) 25 nm-gate-length ZrO2/InAs/InAlAs MOSFETs , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[18]  D-H Kim,et al.  InGaAs MOSFETs for CMOS: Recent advances in process technology , 2013, 2013 IEEE International Electron Devices Meeting.

[19]  D. Caimi,et al.  An integration path for gate-first UTB III-V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling , 2012, 2012 International Electron Devices Meeting.

[20]  J. Alamo.  Nanometre-scale electronics with III–V compound semiconductors , 2011, Nature.

[21]  C. Merckling,et al.  Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm , 2016, 2016 IEEE Symposium on VLSI Technology.

[22]  Maud Vinet,et al.  FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration , 2015 .

[23]  O. Faynot,et al.  3DVLSI with CoolCube process: An alternative path to scaling , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[24]  D. Caimi,et al.  An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).