Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS

Abstract Technology scaling results in that, single event effects, such as single event double-upset due to double-node charge sharing, and single event transient (i.e. an invalid pulse) propagated from upstream combinational blocks, are becoming increasingly serious with technology evolution. In this paper, a single event double-upset fully immune and single event transient filterable latch is proposed in 65 nm CMOS technology. By means of a triple-input Muller C-element, which is driven through a clock gating based triple path DICE, all internal nodes and output node of the latch not only self-recover from single event upset regardless of the energy of a striking particle, but also tolerate single event double-upset when any arbitrary combination of the node pairs is affected. Further, taking advantage of a keeper connected to the output node, the latch is insensitive to a high impedance state. Besides, making use of an embedded Schmitt trigger inverter on the propagation path, the latch also effectively filters single event transient. Simulation results have demonstrated the single event double-upset fully immunity, single event transient filterability, and cost effectiveness, i.e. approximate 60.41% area-power-delay product saving for the latch, compared with the single event double-upset fully immune DNCS-SEI latch, which cannot filter single event transient at all.

[1]  Fabrizio Lombardi,et al.  Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset , 2014, IEEE Transactions on Device and Materials Reliability.

[2]  Ken Choi,et al.  Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology , 2011, Microelectron. Reliab..

[3]  Ken Choi,et al.  Low cost and highly reliable hardened latch design for nanoscale CMOS technology , 2012, Microelectron. Reliab..

[4]  Ken Choi,et al.  High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[6]  Mahdi Fazeli,et al.  Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation , 2013, Microelectron. Reliab..

[7]  Fabrizio Lombardi,et al.  Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  L. W. Massengill,et al.  Single Event Transients in Digital CMOS—A Review , 2013, IEEE Transactions on Nuclear Science.

[9]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[10]  Vojin G. Oklobdzija,et al.  Low-Power Soft Error Hardened Latch , 2009, PATMOS.

[11]  Tianqi Wang,et al.  Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology , 2015, Microelectron. Reliab..

[12]  Huaguo Liang,et al.  A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..

[13]  Sarma B. K. Vrudhula,et al.  A design of a fast and area efficient multi-input Muller C-element , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Lawrence T. Clark,et al.  Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection , 2015, IEEE Transactions on Nuclear Science.

[15]  Kartik Mohanram,et al.  Gate sizing to radiation harden combinational logic , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Xu Hui,et al.  Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches , 2015, IEICE Electron. Express.

[17]  T.M. Mak,et al.  Built-In Soft Error Resilience for Robust System Design , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[18]  Yiorgos Tsiatouhas,et al.  Double node charge sharing SEU tolerant latch design , 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

[19]  Yiorgos Tsiatouhas,et al.  Soft error interception latch: double node charge sharing SEU tolerant design , 2015 .

[20]  J.G. Delgado-Frias,et al.  Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems , 2006, IEEE Transactions on Nuclear Science.

[21]  M. Nicolaidis,et al.  Design for soft error mitigation , 2005, IEEE Transactions on Device and Materials Reliability.

[22]  Huaguo Liang,et al.  A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology , 2015, IEICE Trans. Electron..

[23]  Seyed Nima Mozaffari,et al.  Statistical model for subthreshold current considering process variations , 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

[24]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[25]  Lawrence T. Clark,et al.  Physically Based Predictive Model for Single Event Transients in CMOS Gates , 2016, IEEE Transactions on Electron Devices.

[26]  Russell Tessier,et al.  Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  D. Rossi,et al.  Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.

[28]  Ahmad Patooghy,et al.  Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies , 2009, IET Comput. Digit. Tech..

[29]  Xiaoxuan She,et al.  SEU Tolerant Latch Based on Error Detection , 2012, IEEE Transactions on Nuclear Science.

[30]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[31]  Mahdi Fazeli,et al.  Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations , 2015, J. Circuits Syst. Comput..