论文信息 - Integration of high-Q inductors in a latch-up resistant CMOS technology

Integration of high-Q inductors in a latch-up resistant CMOS technology

Inductors fabricated using CMOS technologies based on epi/p/sup +/ substrates are severely degraded because of eddy current losses in the substrate. We propose and demonstrate a modified substrate structure, which addresses the conflicting goals of high inductor quality-factor and high latch-up immunity. Results include fabricated inductors with Q-factor as high as 16.

[1] S. Voinigescu,et al. SiGe HBT technology: device and application issues , 1995, Proceedings of International Electron Devices Meeting.

[2] Minseok Oh,et al. A 50-GHz 0.25-/spl mu/m implanted-base high-energy implanted-collector complementary modular BiCMOS (HEICBiC) technology for low-power wireless communication VLSIs , 1998, Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198).

[3] D. Edelstein,et al. Monolithic spiral inductors fabricated using a VLSI Cu-damascene interconnect technology and low-loss substrates , 1996, International Electron Devices Meeting. Technical Digest.

[4] J. Long,et al. The modeling, characterization, and design of monolithic inductors for silicon RF IC's , 1997, IEEE J. Solid State Circuits.

[5] I. C. Kizilyalli,et al. Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[6] M. Tsai,et al. The simulation and design of integrated inductors , 1999, DAC '99.

[7] C. Yue,et al. On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's , 1997, Symposium 1997 on VLSI Circuits.