An improved ROM architecture for bubble error suppression in high speed flash ADCs

In high speed flash ADCs, the thermometer coded output of the comparators is converted to binary code by a thermometer-to-binary decoder using a ROM. The ROM is simple and straightforward to design but it requires bubble error correction/suppression circuitry. A novel ROM architecture suitable for high speed operation with bubble error suppression is described in this paper. An 800 MHz 6-bit flash ADC is designed and simulated to verify the performance of different ROM architectures. The proposed ROM architecture eliminates the need of gray encoded ROM as well as gray to binary conversion circuitry, hence reduces the complexity and enhances the performance.

[1]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[2]  C.L. Portmann,et al.  Power-efficient metastability error reduction in CMOS flash A/D converters , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[3]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[4]  Stephen P. Boyd,et al.  Bandwidth extension in CMOS with optimized on-chip inductors , 2000, IEEE Journal of Solid-State Circuits.

[5]  Christopher W. Mangelsdorf.  A 400-MHz input flash converter with error correction , 1990 .

[6]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .

[7]  A. Boni,et al.  A novel coding scheme for the ROM of parallel ADCs, featuring reduced conversion noise in the case of single bubbles in the thermometer code , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[8]  Teresa H. Meng,et al.  Power-efficient metastability error reduction in CMOS flash A/D converters , 1995 .

[9]  K. Uyttenhove,et al.  A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS , 2003, IEEE J. Solid State Circuits.

[10]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).