A 2.5-Gbps De-Skew Chip for Very Short Reach (VSR) Interconnects

We designed and implemented a de-skew chip for parallel optical interconnects. The de-skew ability is limited by the line rate and rising/falling time. We modeled and tested the upper boundary of the maximum allowed channel skew that can be corrected by using this method. This is proved to be a simple and effective way at low line rates at around 2.5 Gbps. For higher line rates, per-pin de-skew scheme is necessary to successfully de-skew all channels with excessive amount of channel skew

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