A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm2.

[1]  Eunseok Song,et al.  A reset-free anti-harmonic delay-locked loop using a cycle period detector , 2004, IEEE Journal of Solid-State Circuits.

[2]  Deog-Kyoon Jeong,et al.  An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance , 2000, IEEE Journal of Solid-State Circuits.

[3]  David J. Foley,et al.  CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[4]  Sung-mo Kang,et al.  A CMOS self-regulating VCO with low supply sensitivity , 2004, IEEE Journal of Solid-State Circuits.

[5]  Beomsup Kim,et al.  A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS , 1999 .

[6]  Chih-Hsing Lin,et al.  A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[7]  Hyoungsik Nam,et al.  A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system , 1998, IEEE J. Solid State Circuits.

[8]  Chulwoo Kim,et al.  Low-power small-area ±7.28 ps jitter 1 GHz DLL-based clock generator , 2002 .

[9]  Hou-Ming Chen,et al.  A Multiphase-Output Delay-Locked Loop With a Novel Start-Controlled Phase/Frequency Detector , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Ching-Che Chung,et al.  A new DLL-based approach for all-digital multiphase clock generation , 2004, IEEE Journal of Solid-State Circuits.

[11]  G. Chien,et al.  A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications , 2000, IEEE Journal of Solid-State Circuits.

[12]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[13]  Chua-Chin Wang,et al.  A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Robert Weigel,et al.  A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12 /spl mu/m standard CMOS , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[15]  Chulwoo Kim,et al.  A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling , 2006, IEEE Journal of Solid-State Circuits.

[16]  Ramesh Harjani,et al.  Design of low-phase-noise CMOS ring oscillators , 2002 .

[17]  Chulwoo Kim,et al.  A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[18]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[19]  Asad A. Abidi,et al.  Phase noise in inverter-based & differential CMOS ring oscillators , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[20]  Bram Nauta,et al.  Low-jitter clock multiplication: a comparison between PLLs and DLLs , 2002 .

[21]  Jaeha Kim,et al.  Adaptive supply serial links with sub-1 V operation and per-pin clock recovery , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[22]  Kyutae Lim,et al.  A ring VCO with wide and linear tuning characteristics for a cognitive radio system , 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

[23]  Shen-Iuan Liu,et al.  A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[24]  William J. Dally,et al.  A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips , 2002, IEEE J. Solid State Circuits.