Temporal analysis of SEU in SOI/GAA SRAMs

This paper analyzes the very strong SEU hardness of a 1k static random-access memory fabricated using the SOI/GAA technology, irradiated with a xenon ion beam at various angles of incidence. The memory has been shown to operate with a supply voltage as low as 2V while still presenting excellent SEU hardness. Since the different physical charge collection mechanisms are particularly slow in SOI devices, it is shown that collected and critical charges must be dynamically compared in order to determine the SEU threshold. A new approach is then proposed to evaluate the time-variable critical charge independently of the pulse shape generated by the incident ion, and a general analytical model is derived. Finally, predictions in good agreement with experimental data are obtained.

[1]  T. Scott,et al.  Fully-depleted submicron SOI for radiation hardened applications , 1994 .

[2]  A. Umbert,et al.  From substrate to VLSI: investigation of hardened SIMOX without epitaxy, for dose, dose rate and SEU phenomena , 1988 .

[3]  J. Colinge,et al.  Some Properties of SOI Gate-All-Around Devices , 1994 .

[4]  S. Furukawa,et al.  Silicon-on-Insulator , 1985 .

[5]  Lloyd W. Massengill,et al.  Effects of process parameter distributions and ion strike locations on SEU cross-section data (CMOS SRAMs) , 1993 .

[6]  R. C. Block,et al.  SEU tests with an improved Cf-252 system , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[7]  R. Harboe-Sorensen,et al.  Test methods for single event upset/latch-up , 1994 .

[8]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[9]  Edward Petersen,et al.  Geometrical factors in SEE rate calculations , 1993 .

[10]  B. Giffard,et al.  SEU in SOI SRAMs-a static model , 1994 .

[11]  N. van Vonno,et al.  A 256 K static random-access memory implemented in silicon-on-insulator technology , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[12]  V. Ferlet-Cavrois,et al.  Heavy ion sensitivity of a SRAM in SOI bulk-like technology , 1993, RADECS 93. Second European Conference on Radiation and its Effects on Components and Systems (Cat. No.93TH0616-3).

[13]  J.A. Seitchik,et al.  Alpha-particle-induced charge transfer between closely spaced memory cells , 1986, IEEE Transactions on Electron Devices.

[14]  R. C. Jaeger,et al.  Analytic Expressions for the Critical Charge in CMOS Static RAM Cells , 1983, IEEE Transactions on Nuclear Science.

[15]  Theodore W. Houston,et al.  An SEU resistant 256 K SOI SRAM , 1992 .

[16]  T. Matsukawa,et al.  Total dose dependence of soft-error hardness in 64 kbit SRAMs evaluated by single-ion microprobe technique , 1994 .

[17]  C. T. Nguyen,et al.  Parasitic bipolar gain in fully depleted n-channel SOI MOSFET's , 1994 .

[18]  M. Alles SPICE analysis of the SEU sensitivity of a fully depleted SOI CMOS SRAM cell , 1994 .

[19]  J. Choma,et al.  Single Event Upset in SOS Integrated Circuits , 1987, IEEE Transactions on Nuclear Science.

[20]  R. L. Woodruff,et al.  Three-dimensional numerical simulation of single event upset of an SRAM cell , 1993 .

[21]  T. R. Weatherford,et al.  The shape of heavy ion upset cross section curves (SRAMs) , 1993 .

[22]  M. Xapsos Applicability of LET to single events in microelectronic structures , 1992 .

[23]  G. E. Davis,et al.  Transient Radiation Effects in SOI Memories , 1985, IEEE Transactions on Nuclear Science.

[24]  L.W. Massengill,et al.  Single-event charge enhancement in SOI devices , 1990, IEEE Electron Device Letters.

[25]  Denis Flandre,et al.  Radiation-hard design for SOI MOS inverters , 1994 .