Study on the Electrical Performance of 80 μm Pitch Bumpless Bonding for Several GHz Interconnections

The major two demands against electronic devices are smaller dimension and higher performance (higher data rate). In terms of packaging technology, flip chip interconnection is one of the currently available solutions that meet those demands by providing high density and low inductance interconnection between chip and system. However, this technology has a limit for fine pitch, which should be ~10um. As an alternative to achieve finer pitch interconnection, we have investigated bumpless interconnection. In this research, we have succeeded in bonding a Si chip to a flexible substrate. Flexible substrates will enable electronic devices become smaller, and are already used for mobile applications in a large volume. A shortcoming of high-density interconnection is that, cross talk noise will become dominant as the spacing between adjacent signal lines will become smaller. To avoid this problem, we have applied a pair line transmission line structure for the interconnection. We got the electrical performance of 3GHz pulse frequency through as many as 196 bumpless interconnections of daisy chain on this experimental system.