A ferroelectric associative memory technology employing heterogate FGMOS structure

A ferroelectric associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the ferroelectric memory cell to associative processing circuits, a heterogate floating-gate MOS structure has been developed. As a result, nondestructive reading of analog data written in the ferroelectric film has been made possible, allowing a wide voltage range of input signals to associative processing circuits. The concept has been experimentally verified using fabricated test devices and circuits.

[1]  M. Nagata,et al.  A minimum-distance search circuit using dual-line PWM signal processing and charge-packet counting techniques , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[2]  Faouzi Kossentini,et al.  Real-time implementation of full-search vector quantization on a low memory SIMD architecture , 1996, Proceedings of Data Compression Conference - DCC '96.

[3]  Y. Tarui,et al.  Future DRAM development and prospects for ferroelectric memories , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[4]  M. Ogawa,et al.  NMOS-based gaussian-element-matching analog associative memory , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[5]  Tadashi Shibata,et al.  Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology , 2001, NIPS.

[6]  Tadashi Shibata,et al.  Neuron-MOS correlator based on Manhattan distance computation for event recognition hardware , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[7]  Shu-Yau Wu,et al.  A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor , 1974 .

[8]  H. Onodera,et al.  A Memory-based Parallel Processor for Vector Quantization , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[9]  Asad A. Abidi,et al.  An 8 b CMOS vector A/D converter , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[10]  H. Ishiwara,et al.  Ferroelectric neuron integrated circuits using SrBi/sub 2/Ta/sub 2/O/sub 9/-gate FET's and CMOS Schmitt-trigger oscillators , 2000 .

[11]  H. Ishiwara,et al.  30-day-long Data Retention in Ferroelectric-gate FETs with HfO2 Buffer Layers , 2004 .

[12]  G. Cauwenberghs,et al.  A Charge-Based CMOS Parallel Analog Vector Quantizer , 1994, NIPS 1994.

[13]  T. Shibata,et al.  A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[14]  T. Shibata Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model , 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[15]  B. A. Minch,et al.  A floating-gate MOS learning array with locally computed weight updates , 1997 .

[16]  T. Morimoto,et al.  A fully-parallel vector quantization processor for real-time motion picture compression , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[17]  A. Sheikholeslami,et al.  A survey of behavioral modeling of ferroelectric capacitors , 1997, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control.

[18]  R. Canegallo,et al.  55GCPS CAM using 5b analog flash , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[19]  James E. Fowler,et al.  Real-time video compression using differential vector quantization , 1995, IEEE Trans. Circuits Syst. Video Technol..

[20]  Belle W. Y. Wei,et al.  A VLSI architecture for a real-time code book generator and encoder of a vector quantizer , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[21]  Tadashi Shibata,et al.  A fast self-convergent flash-memory programming scheme for MV and analog data storage , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[22]  C. Diorio A p-channel MOS synapse transistor with self-convergent memory writes , 2000 .

[23]  H. Van Tran,et al.  A 2.5 V 256-level non-volatile analog storage device using EEPROM technology , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[24]  Tadashi Shibata,et al.  Neuron MOS winner-take-all circuit and its application to associative memory , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[25]  羽生 貴弘 Multiple-valued content-addressable memory using metal-ferroelectric-semiconductor FETs , 1999 .

[26]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[27]  Hidemi Takasu,et al.  A single-transistor ferroelectric memory cell , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[28]  Takashi Nakamura,et al.  Properties of Ferroelectric Memory FET Using Sr2(Ta, Nb)2O7 Thin Film , 1998 .

[29]  C. B. Sawyer,et al.  Rochelle Salt as a Dielectric , 1930 .

[30]  Allen Gersho,et al.  Vector quantization and signal compression , 1991, The Kluwer international series in engineering and computer science.

[31]  Kiyoto Ito,et al.  A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture , 2002 .

[32]  Tadashi Shibata,et al.  A Compact Memory-Merged Vector-Matching Circuitry for Neuron-MOS Associative Processor (Special Issue on Integrated Electronics and New System Paradigms) , 1999 .

[33]  H. Ishiwara,et al.  Memory operations of 1T2C-type ferroelectric memory cell with excellent data retention characteristics , 2001 .

[34]  J. L. Moll,et al.  A new solid state memory resistor , 1963 .

[35]  M. Ikeda,et al.  A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture , 2004, IEEE Journal of Solid-State Circuits.

[36]  M. Lanzoni,et al.  A novel approach to controlled programming of tunnel-based floating-gate MOSFETs , 1994 .