An efficient hardware implementation of MQ decoder of the JPEG2000

Abstract JPEG2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG2000 standard has not only better not only has better compression ratios, but it also offers some exciting features. As it’s hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The MQ decoder of the JPEG2000 standard is an important bottleneck for real-time applications. In order to meet the real-time requirement we propose in this paper a novel architecture for a MQ decoder with high throughput which is comparable to that of other architectures and suitable for chip implementation. This architecture has been implemented in VHDL hardware description language and synthesized using Xilinx’s and Altera’s design flows respectively ISE 13.1 and Quartus. The implementation results show that the design operates at 439.5 MHz when implemented on Virtex-6 and the estimated frame rate at this frequency is 63.24 frames per second (FPS). On Stratix III device, the design operates at 214.4 MHz and the hardware cost is very low. Hardware overhead is minimized to a great extent because the structure of the probability estimation table (PET) is replaced by a small PET ROM. The memory bits used in the architecture are reduced significantly. The use of a dedicated probability estimation table decreases the internal memory.