An adaptive dictionary encoding scheme for SOC data buses

As bus lengths on multi-hundred-million transistor SOCs (systems-on-a-chip) grow and as inter-wire capacitances of sub-0.1 /spl mu/m technologies increase, the resulting high switching capacitances of buses (and interconnects in general) have a non-negligible impact on the power consumption of a whole SOC. In this paper, we address this problem by introducing our bus encoding technique 'ADES' that minimizes the power consumption of data buses through a dictionary-based encoding technique. We show that our technique saves between 18% and 40% of bus energy compared to the non-encoded cases using a large set of (freely-accessible) real-world applications. Furthermore, we compare our technique to the best-known data bus encoding techniques to date and show that it exceeds all of them in energy savings for the same set of applications. The additional hardware effort for our bus en/decoder is thereby very small.

[1]  Naresh R. Shanbhag,et al.  A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Sung-Mo Kang,et al.  Coupling-driven signal encoding scheme for low-power interface design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[4]  Tomás Lang,et al.  Extension of the working-zone-encoding method to reduce the energy on the microprocessor data bus , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[5]  Mircea R. Stan,et al.  Low-power encodings for global communication in CMOS VLSI , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[6]  M.D. Ercegovac,et al.  Effect of wire delay on the design of prefix adders in deep-submicron technology , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[7]  Nikil D. Dutt,et al.  Low-power memory mapping through reducing address bus activity , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Jorg Henkel,et al.  A/sup 2/BC: adaptive address bus coding for low power deep sub-micron designs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Enrico Macii,et al.  Low-energy encoding for deep-submicron address buses , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[10]  Anantha Chandrakasan,et al.  Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[11]  Dietmar Müller,et al.  Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses , 2000, PATMOS.

[12]  Luca Benini,et al.  Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.

[13]  Khalid Sayood,et al.  Introduction to Data Compression , 1996 .

[14]  Tomás Lang,et al.  Working-zone encoding for reducing the energy in microprocessor address buses , 1998, IEEE Trans. Very Large Scale Integr. Syst..