A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer

This paper presents a codesign environment for the UltraSONIC reconfigurable computing platform which is designed specifically for real-time video applications. A codesign environment with automatic partitioning and scheduling between a host microprocessor and a number of reconfigurable processors is described. A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our system is demonstrated with an FFT application.

[1]  Ranga Vemuri,et al.  Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  John J. Granacki,et al.  DEFACTO: A Design Environment for Adaptive Computing Technology , 1999, IPPS/SPDP Workshops.

[3]  Michael J. Flynn,et al.  PAM-Blox: high performance FPGA design for adaptive computing , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[4]  Giovanni De Micheli,et al.  Computer-aided hardware-software codesign , 1994, IEEE Micro.

[5]  Luciano Lavagno,et al.  Hardware-Software Co-Design of Embedded Systems , 1997 .

[6]  Nacer-Eddine Zergainoh,et al.  Multilanguage design of heterogeneous systems , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[7]  Gaetano Borriello,et al.  The Chinook hardware/software co-synthesis system , 1995 .

[8]  W. Kever,et al.  A low-cost graphics and multimedia workstation chip set , 1994, IEEE Micro.

[9]  Petru Eles,et al.  Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[10]  Theerayod Wiangtong,et al.  Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System , 2003, FPL.

[11]  Rolf Ernst,et al.  Codesign of Embedded Systems: Status and Trends , 1998, IEEE Des. Test Comput..

[12]  Ranga Vemuri,et al.  Hardware-software partitioning and pipelined scheduling of transformative applications , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Theerayod Wiangtong,et al.  Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign , 2002, Des. Autom. Embed. Syst..

[14]  S. D. Haynes,et al.  UltraSONIC: A Reconfigurable Architecture for Video Image Processing , 2002, FPL.

[15]  Wayne Wolf,et al.  Process partitioning for distributed embedded systems , 1996, Proceedings of 4th International Workshop on Hardware/Software Co-Design. Codes/CASHE '96.

[16]  Petru Eles,et al.  Design optimization of mixed time/event-triggered distributed embedded systems , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).