Universal Charge-Conserving TFET SPICE Model Incorporating Gate Current and Noise

An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.

[1]  R.P. Jindal,et al.  Compact Noise Models for MOSFETs , 2006, IEEE Transactions on Electron Devices.

[2]  D. E. Nikonov,et al.  Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[3]  Qin Zhang,et al.  Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.

[4]  Hao Lu,et al.  Universal analytic model for tunnel FET circuit simulation , 2015 .

[5]  S. Datta,et al.  On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors , 2009, IEEE Electron Device Letters.

[6]  Ian Young.  IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Launches , 2015 .

[7]  Chenming Hu,et al.  MOSFET Modeling & BSIM3 User’s Guide , 1999 .

[8]  Sorin Cristoloveanu,et al.  Low-frequency noise behavior of tunneling field effect transistors , 2010 .

[9]  Yue Yang,et al.  Tunneling Field-Effect Transistor: Capacitance Components and Modeling , 2010, IEEE Electron Device Letters.

[10]  Gerhard Klimeck,et al.  Polarization-Engineered III-Nitride Heterojunction Tunnel Field-Effect Transistors , 2015, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits.

[11]  Jin He,et al.  An Analytical Charge Model for Double-Gate Tunnel FETs , 2012, IEEE Transactions on Electron Devices.

[12]  P. Asbeck,et al.  Projected Performance of Heterostructure Tunneling FETs in Low Power Microwave and mm-Wave Applications , 2015, IEEE Journal of the Electron Devices Society.

[13]  A. Seabaugh,et al.  Tunnel Field-Effect Transistors: State-of-the-Art , 2014, IEEE Journal of the Electron Devices Society.

[14]  S. Datta,et al.  Flicker noise characterization and analytical modeling of homo and hetero-junction III–V tunnel FETs , 2012, 70th Device Research Conference.

[15]  Dmitri E. Nikonov,et al.  Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking , 2013, Proceedings of the IEEE.

[16]  Mansun Chan,et al.  SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports , 2014, IEEE Transactions on Electron Devices.

[17]  S. Datta,et al.  Electrical Noise in Heterojunction Interband Tunnel FETs , 2014, IEEE Transactions on Electron Devices.

[18]  Andreas Offenhäusser,et al.  Low frequency noise in strained silicon nanowire array MOSFETs and Tunnel-FETs , 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

[19]  Ru Huang,et al.  Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[20]  Chenming Hu,et al.  MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations , 2003 .

[21]  D. Esseni,et al.  Continuous semiempirical model for the current-voltage characteristics of tunnel fets , 2014, 2014 15th International Conference on Ultimate Integration on Silicon (ULIS).

[22]  J. Hoyt,et al.  Microwave detection performance of In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunnel field-effect transistors , 2016 .

[23]  M. J. Kumar,et al.  Impact of gate leakage considerations in tunnel field effect transistor design , 2014, 1406.1319.

[24]  C. Hu,et al.  Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling , 2001 .