High performance SEED processors

Currently, information security is an important issue in our information society and technology. We propose two efficient architectures for processing the 128 bit SEED block cipher using a 32 bit data bus. We compare the proposed architectures with the conventional SEED processor. The proposed SEED processors improve speed and reduce hardware resources using only one G-function in the F-function and the key scheduler of SEED. The operation of the proposed methods has been verified with functional simulation, synthesis and tested on board. The proposed architecture is suitable for hardware-critical applications, such as smart card, PDA, mobile phone, etc.

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