Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model

In this paper, we propose a methodology to perform early design stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW Platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an early design stage before the system design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).

[1]  Kimberly Ryan,et al.  Cadence Design Systems Inc. , 1993 .

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  A compilation-based software estimation scheme for hardware/software co-simulation , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[3]  Daniel Gajski,et al.  Transaction based design: another buzzword or the solution to a design problem? , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[4]  Gabriela Nicolescu,et al.  Component-based design approach for multicore SoCs , 2002, DAC '02.

[5]  Mark A. Gonzales,et al.  Abstract rtos modelling in systemc , 2002 .

[6]  Andreas Gerstlauer,et al.  RTOS modeling for system level design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Andrew S. Tanenbaum,et al.  Structured Computer Organization , 1976 .