A new solution of coherence protocol for tightly coupled multiprocessor systems

Abstract The cache memories used in a multiprocessor system reduce the average access time to the shared memory and, moreover, minimize the bus requirements for each processor. The performance analysis of this multiprocessor showed that: (i) the performance depends on the percentage of write operations operating on shared copies and (ii) some events (such as process migration, execution of input/output interrupt routines on different processors, and so on) create a high number of shared copies derived from memory blocks belonging to private data of processes. By starting from these results, we have designed a new coherence protocol which works to reduce the number of shared copies.

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