A 25-ns low-power full-CMOS 1-Mbit (128 K*8) SRAM

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 mu W in standby mode. The chip is made in a 0.7- mu m twin-tub, single-poly, double-metal technology on p/p/sup +/ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part. >

[1]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[2]  H. Shinohara,et al.  A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM , 1983, IEEE Journal of Solid-State Circuits.

[3]  Tetsuya Iizuka,et al.  A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines , 1987 .

[4]  C. D. Hartgring,et al.  A 40-ns/100-pF low power full-CMOS 256 K (32 K/spl times/8) SRAM , 1987 .

[5]  K. Hardee,et al.  A 30ns 64K CMOS RAM , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  A. Jonkers,et al.  A 1M SRAM with full CMOS cells fabricated in a 0.7µm technology , 1987, 1987 International Electron Devices Meeting.

[7]  S. Kayano,et al.  A 34-ns 1-Mbit CMOS SRAM using triple polysilicon , 1987 .