Advanced Encryption Standard (AES) implementation on FPGA with hardware in loop

In cryptography, Advanced Encryption Algorithm (AES) is a computer security standard defined by National Institute of Standards & Technology (NIST). It is a symmetric key algorithm which uses block of 128 bits of input data & key with different sizes. The size of key can be 128,192 or 256 bits. This paper explains a hardware platform for implementation of AES algorithm with key size 128 bits. Field Programmable Gate Array (FPGA) Artix 7 Nexys 4 kit is used to perform the algorithm by configuring it with the help of Software Development Kit (SDK) in Xilinx ISE design suite. Microblaze is the soft core processor used for the interface between hardware & software. The data is transmitted to the FPGA with the help of MATLAB.