What does ultra low power requirements mean for side-channel secure cryptography?

The design of low power and side-channel-attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel resistance. On one hand, low-power encryption architecture can be more vulnerable to power-attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-attack resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.

[1]  Arijit Raychowdhury,et al.  5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Sanu Mathew,et al.  340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS , 2015, IEEE Journal of Solid-State Circuits.

[3]  Sanu Mathew,et al.  Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines , 2016, ISLPED.

[4]  Vivek De,et al.  Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[5]  Sri Parameswaran,et al.  MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[6]  Christophe Clavier,et al.  Correlation Power Analysis with a Leakage Model , 2004, CHES.

[7]  David Blaauw,et al.  Secure AES engine with a local switched-capacitor current equalizer , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Jens-Peter Kaps,et al.  DPA Resistant AES on FPGA Using Partial DDL , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[9]  Monodeep Kar,et al.  Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators , 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

[10]  Kevin G. Stawiasz,et al.  5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[11]  Sanu Mathew,et al.  340mV–1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[12]  Sun Yihe,et al.  An AES chip with DPA resistance using hardware-based random order execution , 2012 .

[13]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[14]  Fabrice Paillet,et al.  FIVR — Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs , 2014, 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014.

[15]  Habib Mehrez,et al.  Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[16]  Keith A. Bowman,et al.  A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance , 2013, IEEE Journal of Solid-State Circuits.

[17]  Saurabh Dighe,et al.  A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[18]  David Novo,et al.  An EDA-friendly protection scheme against side-channel attacks , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).