A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.

[1]  Eric Andre,et al.  A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  P.R. Gray,et al.  An integrated NMOS operational amplifier with internal compensation , 1976, IEEE Journal of Solid-State Circuits.

[3]  L. Kushner,et al.  A process-scalable low-power charge-domain 13-bit pipeline ADC , 2008, 2008 IEEE Symposium on VLSI Circuits.

[4]  A. N. Karanicolas A 2.7-V 300-MS/s track-and-hold amplifier , 1997 .

[5]  Jan Craninckx,et al.  A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Ian Galton,et al.  A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction , 2009, IEEE Journal of Solid-State Circuits.

[7]  I. Galton,et al.  A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC , 2004, IEEE Journal of Solid-State Circuits.

[8]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[9]  Piet Wambacq,et al.  Distortion analysis of analog integrated circuits , 1998 .

[10]  M. Hesener A 14b 40 MS/s redundant SAR ADC with 480 MHz clock in 0.13μm CMOS , 2007 .

[11]  S. Devarajan,et al.  A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC , 2009, IEEE Journal of Solid-State Circuits.

[12]  Stephen H. Lewis,et al.  Digital background calibration for memory effects in pipelined analog-to-digital converters , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Jan Mulder,et al.  An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[14]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[15]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[16]  Geert Van der Plas,et al.  A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS , 2008, IEEE Journal of Solid-State Circuits.

[17]  Paul Wilkins,et al.  A 16b 125MS/s 385mW 78.7dB SNR CMOS pipeline ADC , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[18]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[19]  U. Langmann,et al.  A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC , 1997 .

[20]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[21]  Yasuhiro Sugimoto,et al.  A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.