BLoG: Post-Silicon bug localization in processors using bug localization graphs

Post-silicon bug localization — the process of identifying the location of a detected hardware bug and the cycle(s) during which the bug produces error(s) — is a major bottleneck for complex integrated circuits. Instruction Footprint Recording and Analysis (IFRA) is a promising post-silicon bug localization technique for complex processor cores. However, applying IFRA to new processor microarchitectures can be challenging due to the manual effort required to implement special microarchitecture-dependent analysis techniques for bug localization. This paper presents the Bug Localization Graph (BLoG) framework that enables application of IFRA to new processor microarchitectures with reduced manual effort. Results obtained from an industrial microarchitectural simulator modeling a state-of-the-art complex commercial microarchitecture (Intel Nehalem, the foundation for the Intel Core™ i7 and Core™ i5 processor families) demonstrate that BLoG-assisted IFRA enables effective and efficient post-silicon bug localization for complex processors with high bug localization accuracy at low cost.

[1]  Srikanth Venkataraman,et al.  Automated Debug of Speed Path Failures Using Functional Tests , 2009, 2009 27th IEEE VLSI Test Symposium.

[2]  Edward J. McCluskey,et al.  Control-flow checking by software signatures , 2002, IEEE Trans. Reliab..

[3]  David J. Lu.  Watchdog Processors and Structural Integrity Checking , 1982, IEEE Transactions on Computers.

[4]  Janak H. Patel,et al.  Architectural level test generation for microprocessors , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  No License,et al.  Intel ® 64 and IA-32 Architectures Software Developer ’ s Manual Volume 3 A : System Programming Guide , Part 1 , 2006 .

[6]  Nicola Nicolici,et al.  Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation , 2008, 2008 Design, Automation and Test in Europe.

[7]  T. Mudge,et al.  High-level test generation for design verification of pipelined microprocessors , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[8]  Don Douglas Josephson,et al.  Debug methodology for the McKinley processor , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[9]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  Subhasish Mitra,et al.  Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA) , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[12]  Doug Josephson,et al.  The good, the bad, and the ugly of silicon debug , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Priyadarsan Patra.  On the cusp of a validation wall , 2007, IEEE Design & Test of Computers.

[14]  John P. Hayes,et al.  High-level test generation for design verification of pipelined microprocessors , 1999, DAC '99.

[15]  Ismet Bayraktaroglu,et al.  Microprocessor silicon debug based on failure propagation tracing , 2005, IEEE International Conference on Test, 2005..

[16]  W. Kent Fuchs,et al.  Dynamic diagnosis of sequential circuits based on stuck-at faults , 1996, Proceedings of 14th VLSI Test Symposium.

[17]  Jacob A. Abraham,et al.  A novel functional test generation method for processors using commercial ATPG , 1997, Proceedings International Test Conference 1997.

[18]  Daniel Gajski,et al.  Generic Architecture Description for Retargetable Compilation and Synthesis of Application-Specific Pipelined IPs , 2006, 2006 International Conference on Computer Design.

[19]  Eli Chiprout,et al.  A microarchitecture-based framework for pre- and post-silicon power delivery analysis , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).