Design and Implementation of High-Performance Memory Systems for Future Packet Buffers

In this paper we address the design of a future high-speedrouter that supports line rates as high as OC-3072 (160 Gb/s),around one hundred ports and several service classes. Buildingsuch a high-speed router would raise many technological problems,one of them being the packet buffer design, mainly becausein router design it is important to provide worst-case bandwidthguarantees and not just average-case optimizations.A previous packet buffer design provides worst-case bandwidthguarantees by using a hybrid SRAM/DRAM approach. Next-generationrouters need to support hundreds of interfaces (i.e.,ports and service classes). Unfortunately, high bandwidth for hundredsof interfaces requires the previous design to use large SRAMswhich become a bandwidth bottleneck. The key observation wemake is that the SRAM size is proportional to the DRAM accesstime but we can reduce the effective DRAM access time by overlappingmultiple accesses to different banks, allowing us to reduce theSRAM size. The key challenge is that to keep the worst-case bandwidthguarantees we need to guarantee that there are no bank conflictswhile the accesses are in flight. We guarantee bank conflictsby reordering the DRAM requests using a modern issue-queue-likemechanism. Because our design may lead to fragmentationof memory across packet buffer queues, we propose to share theDRAM space among multiple queues by renaming the queue slots.To the best of our knowledge, the design proposed in this paper isthe fastest buffer design using commodity DRAM to be publishedto date.