A Multi-Granularity Power Modeling Methodology for Embedded Processors

With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on the OpenRISC and MIPS processors demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/instruction set simulator models that can be used in transaction level models, to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

[1]  Vittorio Zaccaria,et al.  Reducing the complexity of instruction-level power models for VLIW processors , 2005, Des. Autom. Embed. Syst..

[2]  Nikil D. Dutt,et al.  System level power estimation methodology with H.264 decoder prediction IP case study , 2007, 2007 25th International Conference on Computer Design.

[3]  Patrick Girard,et al.  Test power: a big issue in large SOC designs , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

[4]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[5]  W. Nebel.  System-level power optimization , 2004 .

[6]  C. Chakrabarti,et al.  Instruction level power model of microcontrollers , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[7]  Nikil D. Dutt,et al.  Methodology for multi-granularity embedded processor power model generation for an ESL design flow , 2008, CODES+ISSS '08.

[8]  BurgerDoug,et al.  The SimpleScalar tool set, version 2.0 , 1997 .

[9]  Anastasis A. Sofokleous,et al.  Review: H.264 and MPEG-4 Video Compression: Video Coding for Next-generation Multimedia , 2005, Comput. J..

[10]  Holger Blume,et al.  Power estimation on functional level for programmable processors , 2005 .

[11]  Iain E. G. Richardson,et al.  H.264 and MPEG-4 Video Compression: Video Coding for Next-Generation Multimedia , 2003 .

[12]  Mary Jane Irwin,et al.  Techniques for low energy software , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[13]  Sharad Malik,et al.  Power analysis and minimization techniques for embedded DSP software , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Sharad Malik,et al.  Instruction level power analysis and optimization of software , 1996, Proceedings of 9th International Conference on VLSI Design.

[15]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[16]  Karam S. Chatha,et al.  A power and performance model for network-on-chip architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[17]  Vittorio Zaccaria,et al.  Instruction-level power estimation for embedded VLIW cores , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).

[18]  Bruce Jacob,et al.  Instruction-level power dissipation in the Intel XScale embedded microprocessor , 2005, IS&T/SPIE Electronic Imaging.

[19]  Margaret Martonosi,et al.  Full-system chip multiprocessor power evaluations using FPGA-based emulation , 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

[20]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[21]  Patrick Schaumont,et al.  Secure FPGA circuits using controlled placement and routing , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[22]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[23]  Th. Laopoulos,et al.  Measurements analysis of the software-related power consumption in microprocessors , 2003, IMTC 2003.

[24]  Catherine H. Gebotys,et al.  An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors , 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

[25]  Nikil D. Dutt,et al.  System-level power-performance trade-offs in bus matrix communication architecture synthesis , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[26]  D. Sarta,et al.  A data dependent approach to instruction level power estimation , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[27]  Peng Yang,et al.  PowerViP: SoC power estimation framework at transaction level , 2006, Asia and South Pacific Conference on Design Automation, 2006..