A prototype tool for optimum analog sizing using simulated annealing

A prototype tool is described which combines electrical simulation and statistical optimization for the automatic sizing of analog building blocks. A cost function structure is proposed to map a set of specification targets into a combinatorial optimization problem which was solved by statistical methods. The applicability of the tool is demonstrated via several examples. In particular, the design of the building blocks is considered for a 2 mu m CMOS 16 b 20 kHz second-order sigma-delta modulator.<<ETX>>

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