论文信息 - Parallelization of the channel width search for FPGA routing

Parallelization of the channel width search for FPGA routing

As the FPGA becomes more resourceful year by year, the implementation process becomes longer. In particular , the routing process requires a large portion of the implementation, because the routing patterns increase substantially to realize this exibility. Therefore, to reduce the routing process time, we propose a parallel algorithm for the channel-width search in FPGA routing. This algorithm avoids deterioration of cost functions such as delay and routability because each channel-width search is independent. As a result, we achieve a speedup that is 10.56 times the maximum and 4.18 times the average improvement without cost deterioration on 16 processors.

Masahiro Iida | Motoki Amagasaki | Morihiro Kuga | Toshinori Sueyoshi | Hiroomi Sawada

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