VLSI Designs for Multiplication over Finite Fields GF (2m)

The finite fields GF(2m) play a central role in the implementation of BCH/Reed-Solomon coders and decoders. Also, these fields are attractive in some data encryption systems. In this paper we describe a method for designing a parallel multiplier for GF(2m) that is both speed and area efficient. The multiplier proposed is based on the conventional (or polynomial) base representation. From our multiplier we can derive the one introduced by Bartee and Schneider [9]. Their multiplier has been considered unsuitable for VLSI because of lack of modularity. Our approach shows that this multiplier is indeed modular and can also exhibit a high degree of regularity. It is thus well suited for VLSI. Compared to the best parallel design available today, our design requires, roughly, only half the number of gates and still achieves a high operational speed. The speed, size and regularity of our design depends on the irreducible polynomial used to generate the field. In the paper we derive two simple selection criteria for choosing the irreducible polynomial in order to obtain a good design. Also, we present a list of best polynomials for m≤16.