Testing embedded RAMs in ASIC chips

The problems, issues, and solutions for testing RAMs which are embedded in ASIC chips are presented. Testing RAMs requires a test strategy different from that used to test random logic because RAMs have more fault types. In general, for a given fault model such as the stuck-at one/zero model, testing a RAM requires more test vectors than testing a random-logic circuit of the same number of equivalent gates. Embedded RAMs are even more difficult to test because of the limited access to the original nodes of the RAMs.<<ETX>>