论文信息 - The stabilized reference-line (SRL) technique for scaled DRAMs

The stabilized reference-line (SRL) technique for scaled DRAMs

The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs. >

[1] Hideto Hidaka,et al. Twisted bit-line architectures for multi-megabit DRAMs , 1989 .

[2] K. Tsuchida,et al. The stabilized reference-line (SRL) technique for scaled DRAMs , 1989, Symposium 1989 on VLSI Circuits.

[3] Kiyoo Itoh,et al. A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure , 1988 .

[4] Toshio Takeshima,et al. Scaled Bit Line Capacitance Analysis Using a Three-Dimensional Simulator , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.