MULTIPROCESSOR EMULATION WITH RPM: EARLY EXPERIENCE

Field-Programmable Gate Arrays is an emerging technology which promises easy hardware reconfigurability by software at low cost. Entire systems can be built in which some parts are easily programmable. Such systems are flexible hardware platforms or emulators, which are then tailored to implement various architectures. The performance of these architectures can be compared on the same hardware substrate. Besides having a large speedup advantage over software simulation, the emulator is a detailed hardware implementation of the architecture --including I/O-on which complex software systems can be run without code instrumentation and it is a more convincing proof of concept. On the other hand it is much more cost-effective than a full-fledged prototype. We have built a multiprocessor emulator called RPM --Rapid Prototyping engine for Multiprocessor systems. RPM can emulate various configurations of shared-memory and message-passing systems. The bandwidth and latency of various components can be easily modified to match various processor, memory and interconnect technologies. In this paper, we present the modeling methodology, the performance collection mechanism, the calibration of the emulator as well as our first results obtained for the emulator of a cachecoherent non uniform memory access multiprocessor (CC-NUMA).

[1]  Paul Hudak,et al.  Memory coherence in shared virtual memory systems , 1986, PODC '86.

[2]  Anoop Gupta,et al.  The Stanford Dash multiprocessor , 1992, Computer.

[3]  S. Trimberger,et al.  A reprogrammable gate array and applications , 1993 .

[4]  Herb Schwetman,et al.  CSIM: a C-based process-oriented simulation language , 1986, WSC '86.

[5]  R. M. Fujimoto,et al.  Parallel discrete event simulation , 1989, WSC '89.

[6]  John L. Hennessy,et al.  Multiprocessor Simulation and Tracing Using Tango , 1991, ICPP.

[7]  James R. Larus,et al.  The Wisconsin Wind Tunnel: virtual prototyping of parallel computers , 1993, SIGMETRICS '93.

[8]  Per Stenström,et al.  The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors , 1993, [1993] Proceedings 26th Annual Simulation Symposium.

[9]  Michel Dubois,et al.  Essential Misses and Data Traffic in Coherence Protocols , 1995, J. Parallel Distributed Comput..

[10]  Michel Dubois,et al.  Performance Evaluation of the Slotted Ring Multiprocessor , 1995, IEEE Trans. Computers.

[11]  Duncan A. Buell,et al.  Splash 2 , 1992, SPAA.

[12]  Michel Dubois,et al.  RPM: A Rapid Prototyping Engine for Multiprocessor Systems , 1995, Computer.

[13]  Michel Dubois,et al.  The Design of RPM: An FPGA-based Multiprocessor Emulator , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[14]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[15]  William J. Dally,et al.  The J-machine Multicomputer: An Architectural Evaluation , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.

[16]  Erik Hagersten,et al.  DDM - A Cache-Only Memory Architecture , 1992, Computer.

[17]  P. Stenstrom.  A survey of cache coherence schemes for multiprocessors , 1990, Computer.

[18]  Michel Dubois,et al.  Synchronization, coherence, and event ordering in multiprocessors , 1988, Computer.

[19]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[20]  Michel Dubois,et al.  An Integrated Methodology for the Verification of Directory-Based Cache Protocols , 1994, 1994 International Conference on Parallel Processing Vol. 1.

[21]  A. Gupta,et al.  The Stanford FLASH multiprocessor , 1994, Proceedings of 21 International Symposium on Computer Architecture.

[22]  Paul W. A. Stallard,et al.  Parallel evaluation of a parallel architecture by means of calibrated emulation , 1994, Proceedings of 8th International Parallel Processing Symposium.

[23]  A. Veidenbaum,et al.  The cedar system and an initial performance study , 1993, ISCA '93.