Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool

In the last two decades, many efficient algorithms and architectures have been introduced for the design of low-complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low-complexity MCM operations albeit at the cost of an increased delay. In this paper, we address the problem of optimizing the gate-level area in digit-serial MCM designs and introduce high-level synthesis algorithms, design architectures, and a computer-aided design tool. Experimental results show the efficiency of the proposed optimization algorithms and of the digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse response filters.

[1]  Levent Aksoy,et al.  Optimization of area in digit-serial Multiple Constant Multiplications at gate-level , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[2]  A. Dempster,et al.  Use of minimum-adder multiplier blocks in FIR digital filters , 1995 .

[3]  H. T. Nguyen,et al.  Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[4]  K. Steiglitz,et al.  Some complexity issues in digital signal processing , 1984 .

[5]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[6]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[8]  Markus Püschel,et al.  Multiplierless multiple constant multiplication , 2007, TALG.

[9]  Paulo F. Flores,et al.  An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[10]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[11]  Hyeong-Ju Kang,et al.  Digital filter synthesis based on minimal signed digit representation , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[12]  Lars Wanhammar,et al.  Multiple Constant Multiplication for Digit-Serial Implementation of Low Power FIR Filters , 2006 .

[13]  Levent Aksoy,et al.  Search algorithms for the multiple constant multiplications problem: Exact and approximate , 2010, Microprocess. Microsystems.

[14]  R. Hartley.  Subexpression sharing in filters using canonic signed digit multipliers , 1996 .

[15]  A. Dempster,et al.  Constant integer multiplication using minimum adders , 1994 .

[16]  Levent Aksoy,et al.  Optimization of Area in Digital FIR Filters using Gate-Level Metrics , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[17]  P. Barth.  A Davis-Putnam based enumeration algorithm for linear pseudo-Boolean optimization , 1995 .

[18]  Levent Aksoy,et al.  Efficient shift-adds design of digit-serial multiple constant multiplications , 2011, GLSVLSI '11.

[19]  Lars Wanhammar.  DSP integrated circuits , 1999 .

[20]  Ngai Wong,et al.  Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications , 2008, 2008 Asia and South Pacific Design Automation Conference.

[21]  H. Suzuki,et al.  Performance tradeoffs in digit-serial DSP systems , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).

[22]  R. Hartley,et al.  Digit-Serial Computation , 1995 .

[23]  Earl E. Swartzlander,et al.  High radix booth multipliers using reduced area adder trees , 1994, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers.

[24]  A. Dempster,et al.  Multiplication by an integer using minimum adders , 1994 .

[25]  Miodrag Potkonjak,et al.  Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  L. Rabiner,et al.  A computer program for designing optimum FIR linear phase digital filters , 1973 .

[27]  D. H. Jacobsohn,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[28]  A. Rettberg,et al.  Efficient Bit-Serial Constant Multiplication for FPGAs , 2003 .

[29]  O. Gustafsson,et al.  Algorithm to reduce the number of shifts and additions in multiplier blocks using serial arithmetic , 2004, Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference (IEEE Cat. No.04CH37521).

[30]  Levent Aksoy,et al.  Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[31]  W. Marsden.  I and J , 2012 .

[32]  Keshab K. Parhi,et al.  Low-power digit-serial multipliers , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[33]  Keshab K. Parhi.  A systematic approach for design of digit-serial signal processing architectures , 1991 .

[34]  Milos D. Ercegovac,et al.  Digital Arithmetic , 2003, Wiley Encyclopedia of Computer Science and Engineering.

[35]  Peter F. Corbett,et al.  Digit-serial processing techniques , 1990 .

[36]  Lars Wanhammar,et al.  ILP modelling of the common subexpression sharing problem , 2002, 9th International Conference on Electronics, Circuits and Systems.