Hardware bottleneck evaluation and analysis of a software PC-based router
暂无分享,去创建一个
[1] Andrea Bianco,et al. Open-Source PC-Based Software Routers: A Viable Approach to High-Performance Packet Switching , 2005, QoS-IP.
[2] Larry L. Peterson,et al. VERA: an extensible router architecture , 2002, Comput. Networks.
[3] Bernhard Plattner,et al. Router plugins: a software architecture for next generation routers , 1998, SIGCOMM '98.
[4] Jamal Hadi Salim,et al. Beyond Softnet , 2001, Annual Linux Showcase & Conference.
[5] K. K. Ramakrishnan,et al. Eliminating receive livelock in an interrupt-driven kernel , 1996, TOCS.
[6] Tzi-cker Chiueh,et al. Implementation and Evaluation of A QoS-Capable Cluster-Based IP Router , 2002, ACM/IEEE SC 2002 Conference (SC'02).
[7] Giovanni Schembra,et al. Comparative Analysis of SMP Click Scheduling Techniques , 2005, QoS-IP.
[8] Robert Tappan Morris,et al. Flexible Control of Parallelism in a Multiprocessor PC Router , 2001, USENIX Annual Technical Conference, General Track.
[9] Shlomo Weiss,et al. A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations , 2002, J. Syst. Archit..
[10] Eddie Kohler,et al. The Click modular router , 1999, SOSP.
[11] R. Bolla,et al. RFC 2544 performance evaluation and internal measurements for a Linux based open router , 2006, 2006 Workshop on High Performance Switching and Routing.
[12] Mike H. MacGregor,et al. Cluster-based IP Router: Implementation and Evaluation , 2006, 2006 IEEE International Conference on Cluster Computing.
[13] M. Mellia,et al. Click vs. Linux: two efficient open-source IP network stacks for software routers , 2005, HPSR. 2005 Workshop on High Performance Switching and Routing, 2005..
[14] Mark Handley,et al. XORP: an open platform for network research , 2003, CCRV.