A Degree Priority Routing Algorithm for Irregular Mesh Topology NoCs

In this paper, a degree priority routing algorithm is proposed to minimize the hardware cost for nonregular mesh network-on-chip. In the algorithm, the routing path is dynamically selected with respective to the communication status of the next hop node. The next hop node concluded by the degree priority routing different with them obtained by routing algorithm are inserted in the routing table. And, the items in the routing table that have the same contents are combined to further minimize the area and power. Experimental results show that the proposed algorithm has better performance than other three routing algorithms.

[1]  Luca Benini,et al.  Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs , 2003, Proceedings 21st International Conference on Computer Design.

[2]  Karam S. Chatha,et al.  A power and performance model for network-on-chip architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[4]  Manfred Glesner,et al.  Deadlock-free routing and component placement for irregular mesh-based networks-on-chip , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[6]  Jian Liu,et al.  Interconnect intellectual property for Network-on-Chip (NoC) , 2004, J. Syst. Archit..

[7]  Ran Ginosar,et al.  Efficient Routing in Irregular Topology NoCs , 2022 .

[8]  Axel Jantsch,et al.  Networks on chip , 2003 .

[9]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[10]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[11]  Krishnan Srinivasan,et al.  An automated technique for topology and route generation of application specific on-chip interconnection networks , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[12]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[13]  Shashi Kumar,et al.  A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures , 2006, SAMOS.

[14]  Ran Ginosar,et al.  Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip , 2005 .