Markov chain analysis of packet-switched banyans with arbitrary switch sizes, queue sizes, link multiplicities and speedups
暂无分享,去创建一个
[1] Janak H. Patel,et al. Processor-memory interconnections for multiprocessors , 1979, ISCA '79.
[2] Tse-Yun Feng,et al. On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.
[3] Daniel Manuel Dias. Packet communication in delta and related networks , 1981 .
[4] Daniel M. Dias,et al. Analysis and Simulation of Buffered Delta Networks , 1981, IEEE Transactions on Computers.
[5] Janak H. Patel. Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.
[6] Mark A. Franklin,et al. Pin Limitations and Partitioning of VLSI Interconnection Networks , 1982, IEEE Transactions on Computers.
[7] Marc Snir,et al. The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.
[8] Yih-Chyun Jenq,et al. Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network , 1983, IEEE J. Sel. Areas Commun..
[9] Manoj Kumar,et al. Packet switching in N log N multistage networks , 1991 .
[10] Manoj Kumar. PERFORMANCE IMPROVEMENT IN SINGLE-STAGE AND MULTIPLE-STAGE SHUFFLE-EXCHANGE NETWORKS , 1984 .
[11] L. T. Wu. Mixing traffic in a buffered banyan network , 1985, SIGCOMM 1985.
[12] Gregory F. Pfister,et al. A Methodology for Predicting Multiprocessor Performance , 1985, International Conference on Parallel Processing.
[13] Manoj Kumar,et al. Switching Strategies in Shuffle-Exchange Packet-Switched Networks , 1985, IEEE Transactions on Computers.
[14] Ted H. Szymanski,et al. On the Universality of Multistage Interconnection Networks , 1986, International Conference on Parallel Processing.
[15] Alan Weiss,et al. The Distribution of Waiting Times in Clocked Multistage Interconnection Networks , 1988, IEEE Trans. Computers.
[16] Ted H. Szymanski. Interconnection Network Modelling Using Monte Carlo Methods, Markov Chains and Performance Petri Nets , 1987, Computer Performance and Reliability.
[17] Anthony S. Acampora,et al. The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet Switching , 1987, IEEE J. Sel. Areas Commun..
[18] Ted H. Szymanski,et al. On the Permutation Capability of Multistage Interconnection Networks , 1987, IEEE Transactions on Computers.
[19] Hamid Ahmadi,et al. A high-performance switch fabric for integrated circuit and packet switching , 1988, IEEE INFOCOM '88,Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?.
[20] Jonathan S. Turner,et al. Design of a broadcast packet switching network , 1988, IEEE Trans. Commun..
[21] Ted H. Szymanski,et al. On the Universality of Multipath Multistage Interconnection Networks , 1989, J. Parallel Distributed Comput..
[22] Jonathan S. Turner,et al. Nonblocking Multirate Networks , 1989, SIAM J. Comput..
[23] Jonathan S. Turner,et al. Performance of a broadcast packet switch , 1989, IEEE Trans. Commun..