FPGA-in-the-loop-simulations for dynamically reconfigurable applications

This contribution presents a hardware-in-the-loop (HiL) design environment for FPGA-based systems. The presented tool-flow supports a two-stage verification process: A cycle-accurate HiL simulation using well-known simulation tools such as MATLAB/Simulink or Modelsim, and a real-time test using the target environment of the Design Under Test (DUT). The first stage allows an early verification of the DUT using a simulated environment, while the focus of the second stage is on monitoring internal states and I/Os of the DUT in operation, and on adjusting design parameters. All hardware and software interfaces required for both stages are generated individually and automatically by our tool-flow. The demo shows the benefits of using the presented HiL framework for applications targeting dynamic hardware reconfiguration. As an example, a two-controller system for an inverted pendulum is presented, where either a real system or an FPGA-based model combined with an augmented reality 3D animation can be used.