2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration

This paper introduces a hybrid capacitive coupling interconnects (CCIs) array suitable for bumpless flip-chip 3-D integration. Inside the hybrid array, both single-ended and common-centroid differential CCIs are interleaved together to cancel the crosstalk among them. The crosstalk cancellation capability of its own allows CCIs to be placed closer and thus improves the area efficiency. A high gain and high common-mode-rejection ratio receiver is also presented to minimize the jitter caused by the common-mode noise. The process variation track biasing circuit is also proposed for the receiver. The measurement verifies that the proposed transceiver in a 3 × 3 pseudohybrid CCIs array produces only 84 ps or 0.2 unit interval crosstalk related jitter under the worst case crosstalk condition. A total of nine transceivers in the array achieve the data rate of 20.79 Gb/s and consume only 53 μW/Gb/s. The chip was fabricated in 65-nm CMOS technology.

[1]  J. Lau.  Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration , 2011, 2011 International Symposium on Advanced Packaging Materials (APM).

[2]  Mau-Chung Frank Chang,et al.  Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  H. Kawaguchi,et al.  . 7 10 . 7 1 . 27 Gb / s / pin 3 mW / pin Wireless Superconnect ( WSC ) Interface Scheme , 2003 .

[4]  M. Mantysalo,et al.  System design issues for 3D system-in-package (SiP) , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[5]  Tony Tae-Hyoung Kim,et al.  A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs , 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Werner Weber,et al.  Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[7]  Mark Horowitz,et al.  Scaling, Power and the Future of CMOS , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[8]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[9]  Roberto Guerrieri,et al.  3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly , 2007, IEEE Journal of Solid-State Circuits.

[10]  Takushi Hashida,et al.  A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

[11]  R. Guerrieri,et al.  3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities , 2008, IEEE Journal of Solid-State Circuits.

[12]  T. Sakurai,et al.  Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[13]  Roberto Guerrieri,et al.  Characterization of chip-to-chip wireless interconnections based on capacitive coupling , 2010, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip.

[14]  T. Sakurai,et al.  A 195Gb/s 1.2W 3D-stacked inductive inter-chip wireless superconnect with transmit power control scheme , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[15]  Tadahiro Kuroda,et al.  A Wafer test method of inductive-coupling link , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[16]  T. Sakurai,et al.  A High-Speed Inductive-Coupling Link With Burst Transmission , 2009, IEEE Journal of Solid-State Circuits.

[17]  Mitsumasa Koyanagi,et al.  High-Density Through Silicon Vias for 3-D LSIs , 2009, Proceedings of the IEEE.

[18]  Chuan Seng Tan,et al.  Wafer-level hermetic packaging of 3D microsystems with low-temperature Cu-to-Cu thermo-compression bonding and its reliability , 2012 .

[19]  R. Ho,et al.  Proximity communication , 2004, IEEE Journal of Solid-State Circuits.

[20]  N. Miura,et al.  A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS) , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[21]  H. Reichl,et al.  Technologies for 3D wafer level heterogeneous integration , 2008, 2008 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS.

[22]  Tadahiro Kuroda,et al.  3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link , 2010, IEEE Journal of Solid-State Circuits.

[23]  Tony Tae-Hyoung Kim,et al.  Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[24]  Tadahiro Kuroda,et al.  A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[25]  Justin Schauer,et al.  Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[26]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[27]  Robert C. Frye,et al.  Silicon-on-silicon MCMs with integrated passive components , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[28]  A. Sangiovanni-Vincentelli,et al.  Yield Prediction for 3D Capacitive Interconnections , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[29]  T. Sakurai,et al.  Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect , 2005, IEEE Journal of Solid-State Circuits.