论文信息 - A Hierarchical Parallelizing Compiler for VLIW/MIMD Machines

A Hierarchical Parallelizing Compiler for VLIW/MIMD Machines

Hierarchical architectures attempt to provide the benefits of both VLIW/superscalar and MIMD machines by combining multiple VLIW or superscalar processors as parallel, asynchronous processors. An example of these architectures is the Intel Touchstone multicomputer. These machines provide the opportunity to execute a program in parallel at both the machine instruction level and the source statement level.

Alexandru Nicolau | Carrie J. Brownhill | A. Nicolau

[1] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[2] Ron Cytron,et al. Doacross: Beyond Vectorization for Multiprocessors , 1986, ICPP.

[3] Mario G. Salvadori,et al. Numerical methods in FORTRAN , 1965 .

[4] Alexandru Nicolau,et al. Uniform Parallelism Exploitation in Ordinary Programs , 1985, ICPP.

[5] Roni Potasman. Percolation-based compiling for evaluation of parallelism and hardware design trade-offs , 1991 .

[6] Alexander Aiken,et al. Optimal loop parallelization , 1988, PLDI '88.

[7] David Alejandro Padua Haiek. Multiprocessors: discussion of some theoretical and practical problems , 1980 .

[8] Monica S. Lam,et al. A Loop Transformation Theory and an Algorithm to Maximize Parallelism , 1991, IEEE Trans. Parallel Distributed Syst..